Recent advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Semiconductor manufacturing process advancements are driving the corresponding geometric dimensions for semiconductor devices to decreasingly smaller values. As semiconductor device dimensions shrink, the number of devices per unit area of semiconductor die grows. Given higher device densities within a given semiconductor die, a greater opportunity exists that devices, which must interface to one another, operate at incompatible drive levels.
One example of a semiconductor device that is required to operate at various drive levels may be illustrated by an integrated circuit (IC), such as a Field Programmable Gate Array (FPGA). In particular, the FPGA employs a logic core that operates at a fixed voltage supply. As semiconductor manufacturing processes advance, geometries of the semiconductor devices within the logic core decrease, which causes a decrease in threshold voltages of the semiconductor devices. Accordingly, the logic core must operate at decreasing voltage supply magnitudes. For example, as the geometry of the logic core shrinks from 130 nanometer (nm) geometries down to 45 nm geometries, the core voltage supply and logic core device threshold voltage similarly scales to decreasingly lower magnitudes to ensure proper operation.
While logic core voltages decrease, however, the FPGA is nevertheless required to maintain support of a wide range of input/output (I/O) interfaces, which further requires support of a wide power supply range at the I/O interface. Thus, as signals are exchanged between the logic core of the FPGA and the I/O interface portion of the FPGA, level translation is required, so that signals operating at logic core voltage magnitudes may be properly exchanged with the I/O interface, where signals operate at the higher I/O voltage magnitudes.
Level translation between the logic core and the I/O interface portion of the FPGA may be implemented by a cross-coupled latch architecture with feedback. In particular, differential input stages are cross-coupled, such that the logic output of a first stage activates the pull-up portion of the second stage, while the logic output of the second stage deactivates the pull-up portion of the first stage during a first phase of operation. Similar operation of the differential input stage occurs during a second phase of operation.
As a result of decreasing logic core voltages due to decreasing logic core device geometries, the cross-coupled latch fails to resolve itself, or resolves itself slowly, due to inadequate drive level of the cross-coupled feedback signal that originates from a logic core device. Thus, the failure of the cross-coupled latch seems to be linked to the decreasing logic core voltage magnitudes and also seems to be exacerbated by the lower magnitude I/O interface voltage levels.
An improvement to the conventional cross-coupled latch architecture is, therefore, required. In particular, a solution is needed that allows the cross-coupled latch to properly resolve itself across all combinations of I/O interface voltage magnitudes and logic core voltage magnitudes.